Various techniques have be used to integrate more circuit patterns within a limited area of a wafer or a semiconductor substrate. In the case of Dynamic Random Access Memory (DRAM) devices, for example, various techniques have been used to change an arrangement of active regions from an 8F2 cell layout into a 6F2 layout.
DRAM devices typically include bit lines for writing and reading data to and from cells in memory and word lines for selecting the particular cell to which data is written and from which data is read. Bit lines and word line are often arranged perpendicular to each other. The 6F2 cell layout has repeatedly arranged active regions diagonally with respect to the word line. The active region with a diagonal pattern is arranged in a rectangular pattern which extends in a diagonal direction intersecting with the bit line by an angle of about 27°. In this active region, the word line. including a gate intersecting in a diagonal direction by about 63°, with the bit is arranged and the bit line is arranged to be electrically coupled to the active region through a bit line contact and a pad.
A memory cell of the DRAM device includes a single transistor and a single capacitor, and the capacitor is stacked on an upper portion of the bit line. A storage node contact coupled to a storage node of the capacitor is formed penetrating through an insulation layer, passing by the bit line, and is electrically coupled to the active region thereunder through a storage node contact pad prepared in a lower portion of the contact.
Since a gap between the bit lines is much narrowed due to reduction of design rule, it becomes difficult to ensure a process margin for insulation between the storage node contact and the bit line. When forming the storage node contact by a Self Aligned Contact (SAC) process, a wider gap between the bit lines should be ensured to ensure a SAC margin. However, a Critical Dimension (CD) of the bit line should be reduced more in order to ensure the gap between the bit lines, and this reduction in the CD of the bit line can reduce an overlay margin between the bit line and the bit line contact and cause resulting increase in a resistance due to reduction in a contact area.
In order to ensure more overlay margin between the bit line and the bit line contact while reducing the CD of the bit line, a method of designing a layout of the bit line in a shape of a dog bone, in which a middle portion of the bit line to be overlaid with the contact is designed wider than the other portions, can be considered. However, since it is difficult to ensure precision in pattern transfer by a lithography process when a cell design rule of 40 nm or less is applied, it is difficult to precisely form the dog bone shape into a pattern.
Therefore, it is difficult to provide a separation margin, by which a capping layer or a hard mask formed on the bit line can sufficiently separate the contacts, in the SAC process for the storage node contact which is performed after the formation of the bit line. That is to say, it is difficult to form a CD of the capping layer in a sufficient size since it is difficult to pattern transfer the bit line in a form capable of ensuring a sufficient CD and it is accordingly difficult for the capping layer to function as an isolation layer in an etching or polishing process for isolating the contacts from each other in the SAC process. There can be caused defect in that bridge between the contacts is generated due to the insufficient CD of the capping layer or the storage node contact and the bit line contact are interconnected due to the insufficient gap margin therebetween.